1. Field of the Invention
The present invention relates to a data processing system architecture.
2. Description of the Prior Art
It is known to use a so-called bus architecture in data processing systems, where one or more central processors (in multiprocessor systems), a plurality of peripheral controllers and one or more working memories communicate with each other through a common channel or bus to transfer information between such units. The bus architecture, while involving some limitations, is largely used because it allows a wide flexibility in configuring the system to meet user requirements and reduces the number of connection leads among the units. Data processing systems having bus architecture are described in U.S. Pat. Nos. 3,710,324; 4,303,808; and 3,993,981. Bus architecture limitations are mainly caused by three factors:
(1) conflict in the use of the bus by the several units; PA0 (2) synchronization in the operation of the several units; and PA0 (3) electrical propagation of the signals.